`timescale 1ns/1ns

module multi_pipe#(
           parameter size = 4)(
           input clk,
           input rst_n,
           input [size - 1: 0] mul_a,
           input [size - 1: 0] mul_b,
           output reg [size * 2 - 1: 0] mul_out
       );
wire [size * 2 - 1: 0] temp [3: 0];
reg [size * 2 - 1: 0] mul1;
reg [size * 2 - 1: 0] mul2;
genvar i;
generate
	for (i = 0;i < 4;i = i + 1)
		begin:loop
			assign temp[i] = mul_b[i] ? mul_a << i : 4'd0;
		end
endgenerate

always@(posedge clk or negedge rst_n)
	begin
		if (!rst_n)
			mul1 <= 'd0;
		else
			mul1 <= temp[0] + temp[1];
	end

always@(posedge clk or negedge rst_n)
	begin
		if (!rst_n)
			mul2 <= 'd0;
		else
			mul2 <= temp[2] + temp[3];
	end

always@(posedge clk or negedge rst_n)
	begin
		if (!rst_n)
			mul_out <= 'd0;
		else
			mul_out <= mul1 + mul2;
	end
endmodule
